A flash memory device is a nonvolatile high-density data storage device that can write and erase data on-board. A flash memory cell includes a field effect transistor (FET) having a selection gate, a floating gate, a source and a drain. Data is stored in the flash memory cell by variations in the amount of charge stored in the floating gate, which causes a variation in a threshold voltage (Vt) of the flash memory cell. The data stored in the flash memory cell is read out by applying a selection voltage to a word line connected to the selection gate. The amount of current, which flows when the flash memory cell is selected, is determined by the threshold voltage (Vt) of the flash memory cell.
A flash memory cell generally has two states, i.e., “programmed” and “erased.” If the flash memory cell is programmed, excess electrons are trapped on the floating gate and the threshold voltage (Vt) rises, so that only a small amount of drain-source current flows across the flash memory cell when the cell is selected to be read. The programmed state of the flash memory cell is called a logic “0”. If the flash memory cell is erased, there are few or no excess electrons on the floating gate, causing a large amount of source-drain current to flow across the flash memory cell when the cell is selected to be read. The erased state of the flash memory cell is called a logic “1”.
FIG. 1 is a schematic diagram of a conventional flash memory device. Referring to FIG. 1, the conventional flash memory cell 100 includes a memory cell array block 110, a row decoder 120, a word line level selection block 130, a driver block 140, and a page buffer 150. The memory cell array block 110 includes i number of strings 200, 202, 204, and 206, each of which has flash memory cells connected in series with each other. The first string 200 includes flash memory cells 112, 113, and 114 connected in series with each other, whose gates are connected from the first to the sixteenth word lines WLj (j=0, 1, . . . , 15), respectively. The flash memory cell 112, connected to the first word line WL0, has a drain connected to a first selection transistor 111, whose gate is connected to a string selection line SSL. The flash memory cell 114, connected to the sixteenth word line WL15, has a source connected to a second selection transistor 115, whose gate is connected to a ground selection line GSL. The first selection transistor 111 has a drain connected to a first bit line BL0, and the second selection transistor 115 has a source connected to a common source line CSL.
The strings 200, 202, 204, and 206 are connected with the string selection line SSL, the first to sixteenth word lines WLj (j=0, 1, . . . , 15), and the ground selection line GSL. Additionally, each of the strings 200, 202, 204, and 206 is connected to the page buffer 150 through the bit lines BL0, BL1, BLi−1 and BLi to form one page unit. Although FIG. 1 shows only one page unit contained in the memory cell array block 110 for convenience, the memory cell array block 110 can actually include a number of page units. The page units are addressed by the row decoder 120. Transistors contained in the driver block 140 are turned on in response to addressing signals of the row decoder 120, so that one page unit is selected.
The word line level selection block 130 selects a programming voltage VPGM, a read voltage VREAD, a program verification voltage VRDV, or a pass voltage VPASS according to a corresponding mode, and transfers the selected voltage to the driver block 140. The programming voltage VPGM and the read voltage VREAD are applied during the programming operation and the read operation of the selected flash memory cells, respectively. The program verification voltage VRDV is applied to verify whether the flash memory cell is programmed or not. The pass voltage VPASS is applied to make non-selected flash memory cells electrically “turned on” and thus cause a cell current to flow therethrough. The driver block 140 applies the corresponding mode voltage to the word lines WLj (j=0, 1, . . . , 15) of one selected page unit in response to an addressing signal of the row decoder 120. The page buffer 150 senses the cell current flowing through the bit lines BL0, BL1, . . . , BLi−1 and BLi, and interprets data from the selected flash memory cells.
After the programming operation, the flash memory device 100 repeatedly performs a cycle (“program unit loop”) that carries out the program verification operation. As a result of the program verification operation, if it is verified that the flash memory cells are programmed, the programming operation is ended, and if not, the programming operation is carried out once more and the program verification operation is repeated. For example, if a large number of flash memory cells are connected to a single word line, predetermined cycles are required to program all of the flash memory cells and to verify their programs. Once verified that the flash memory cells connected to the selected word line are completely programmed, flash memory cells connected to another word line are programmed and their programs are verified.
If the program operation and the program verification operation are repeatedly performed to one selected word line, a problem may be caused where the programming operation is prematurely ended by misjudging underprogrammed flash memory cells as programmed. The reason is, as shown in FIG. 2, that as the programming voltage VPGM increases and the program verification voltage VRDV is constantly applied during the repeated program unit loops, the cell current increases due to the flash memory cells that are underprogrammed during the first several program unit loops, thereby causing an increase of the level of the common source line CSL. Here, if the program verification voltage VRDV is constantly applied throughout the program unit loops, the cell current decreases due to an increase in the level of the common source line CSL. Accordingly, the flash memory cells that are actually underprogrammed may be misjudged as programmed.
FIG. 3 is a graph of example threshold voltage distributions of flash memory cells during the program verification operation of FIG. 2. Referring to FIG. 3, in an initial state, when the erase operation is performed to all flash memory cells, the threshold voltage (Vt) of the flash memory cells has a negative voltage level. The program unit loops are then sequentially performed and the flash memory cells are programmed by the high programming voltage VPGM at the last loop. As a result, the threshold voltage (Vt) is distributed non-uniformly at the high end. This non-uniform distribution of the high threshold voltage (Vt) causes a problem of overprogramming the flash memory cells of the page unit. Additionally, the flash memory cells having a low threshold voltage (Vt), similar to the program verification voltage VRDV, may remain in an underprogrammed state because it is uncertain whether the flash memory cells are programmed or not.
Embodiments of the invention address these and other limitations in the prior art.